This document is a datasheet of iEthernet W5200 (QFN 48pin package).
Please refer to the attached PDF file.

Ver. 1.2.9:(5APR20)

1.Corrected “Figure 1at 1 Pin Assignment” (P.8)

from MDC/SPIEN to SPIEN, from MDIO to RSV

2.Corrected Table

from MDC/SPIEN to SPIEN at 1.1 MCU Interface Signals(P.10)

from MDIO to RSV at 1.3 MCU Interface Signals(P.10)

Notes: Pull-Up/Down resistor 75k ->10k

3.Corrected “Figure 2,3 at 1.4 Power Supply Signal” (P.11~12)

4. Corrected “Timeout expression at 4.1 Common Registers”(P.20)

5. Updated “Description of SOCK_LAST_ACK at 4.2 Socket Register”(P.30)

Ver. 1.2.8 :(13NOV2012)
1. Updated description of “W5200”(P.2)

2. Added more information about “indirect interface mode at 1.1 MCU Interface Signals”(P.8)

3. Updated “Figure 1 at 1.1 MCU Interface Signals ”(P.8)

corrected Pin6~7, Pin30~39, Pin42~43

4. Updated “pin descriptions at 1.1 MCU Interface Signals”(P.8-13)

5. Updated description of “INTn at 1.1 MCU Interface Signals”(P.9)

Added Sn_IR in description

6. Updated “Socket register at 3.2 Socket registers”(P.16)

corrected from Socket 0 to Socket n

7. Updated description of Table

Added WOL in Table of “Mode register at 4.1 Common Registers” (P.17)

Added MF in Table of “Sn_MR at 4.2 Socket Registers ”(P.24)

8. Updated description of “INTLEVEL at 4.1 Common Registers” (P.21)

9. Corrected “ Figure24 and Table at 7.4.3 SPI Timing”(P.80)

corrected from Tcss(Hold time) to Tcss(Setup time) in Table

10. Corrected Table ,“FSCK and TCHZ at 7.4.3 SPI Timing” (P.80)

FSCK from 80MHz to 80/33.3MHz

TCHZ from 5ns to 2.1ns

11. Corrected typo for:

from registor to resistor in notes at 1.3 Miscellaneous Signals (P.11)

from 1v80 to 1v8O(TYPO) in Table at 1.4 Power Supply Signals(P.11)

from Interrupt Mask to Interrupt at 4.2 Socket Registers (P.29)

from IR to IR2 at 4.1 Common Registers(P.21)

Ver. 1.2.7:(27JULY2012)

1.Updated “Pin names at 1 Pin Assignment” (P.8)

from PowerOut to 1V8O (PIN 14)

2.Changed “IMR address (0x36 to 0x16)” (P14, P.22-> P.18)

3.Changed “IMR2 address (0x16 to 0x36)” (P14, P.18->P.22)

4.Corrected table of “DIPR size format at 4.2 Socket Register” (P.33)

5.Corrected the table and figure of “RX, TX memory size format at 4.2 Socket Register ” (P.35,41)

Ver.1.2.6:(12JULY2012)

1. Corrected value of “memory map at 2 Memory Map” (P.13)

2. Corrected code of “write processing at 6.3 Process of using general SPI Master device” (P.75)

Ver.1.2.5:(12APR2012)
1. Corrected some miss phrase and words.

2. Corrected “Figure18 of SPI frame format at 6.1 SPI mode”(P.72)

Ver.1.2.4:(16FEB2012)
Corrected “Pin names and sequence diagrams of READ processing and WRITE processing at 6.3 Processing of using general SPI Master device” (P.73, 75)

Ver.1.2.3:(3FEB2012)
Added “Figure2 of XTAL_VDD at 1.4 Power Supply Signals” (P.11)

Ver.1.2.2:(25NOV2011)
Corrected “Block Diagram” (P.4)

Ver.1.2.1:(2AUG2011)
Corrected the description of “READ processing at 6.3 Processing of using general SPI Master device ”(P.73)

Ver.1.2.0:(22APR2011)

1. Corrected description of “RSV at 1.3 Miscellaneous Signals” (P.10)

2. Corrected the values of “typical at 7.3 power dissipation” (P.77)

3. Added values of “maximum at 7.3 power dissipation ”(P.77)

4. Removed “PIN31 at 1.3 Miscellaneous Signals” ( P.10)

Ver.1.1.0:(13MAR2011)
1.Changed “IMR address (0x16 to 0x36)” (P.14, P.18)

2.Changed “IMR2 address (0x36 to 0x16)” (P.14, P.22)

Ver.1.0.0:(Mar2011)
Released with W5200 Launching